Program -- SILM 2023, 2023-07-03, with EuroSP in Delft, NL



Time (CEST)   Session
09:00-09:30 Coffee - Introduction
09:30-10:30 Session-1: Microarchitectural Attacks and Defences in Microcontrollers
10:30-11:00 Break (Coffee)
11:00-11:30 Session-1 (cont'd): Microarchitectural Attacks and Defences in Microcontrollers
11:30-12:30 Invited Talk
12:30-14:00 Break (Lunch)
14:00-15:00 Session-2: Attacks and Defences for Crypto Implementations
15:00-15:30 Break (Coffee)
15:30-16:00 Discussion
16:30-17:30 Session-3: Side Channels, Static & Dynamic Analysis
17:30-18:00 Closing Remarks

Call for Papers

Full CfP as text file: silm2023-cfp.txt

Special Theme 2023: SILM for Telecommunications

As a special theme for SILM 2023, we solicit submissions that present novel research that develops or relies on hardware/software interfaces to improve security and dependability in the telecommunications sector. In particular, work that aims at 5G, edge and cloud scenarios where strict requirements on bandwidth, latency, and availability need to be met, are of special interest for SILM this year. Submissions must be within the general scope of SILM 2023 as stated below.

General topics of interest

Topics of interest include, but are not limited to the following:

  • Hardware reverse engineering
  • Microcode security analyses
  • Software side-channel attacks
  • Software attacks against micro-architecture
  • Software-activated fault attacks
  • Hardware-based security mechanisms
  • Software counter-measures against hardware vulnerabilities
  • Formal methods applied to the security of software/hardware interfaces
  • Hardware enclaves
  • Hardware trace mechanisms for security
  • OS and VM introspection

Submission guidelines

We accept two categories of submissions:

  1. Regular papers describing fully developed work and complete results (10 pages, references included, IEEE format)
  2. Short papers, position papers, industry experience reports, work-in- progress submissions and ideas (6 pages, references included, IEEE format; work-in-progress and idea submissions should clearly outline research hypothesis, evaluation strategy and potential impact)

All papers must be written in English and describe original work that has not been published or submitted elsewhere. The submission category (regular paper, short paper, special theme) should be clearly indicated. All submissions will be fully reviewed by members of the Program Committee. Papers will appear in IEEE Xplore in a companion volume to the regular EuroS&P proceedings. Contact the Program Chairs if you do *not* want your *short paper* to appear in the proceedings.

Papers must be typeset in LaTeX in A4 format (not “US Letter”) using the IEEE conference proceeding template we provide: eurosp-2023-template.zip We suggest you first compile the supplied LaTeX source as is, checking that you obtain the same PDF as the one supplied, and then write your paper into the LaTeX template, replacing the boilerplate text. Please do not use other IEEE templates. Failure to adhere to the page limit and formatting requirements can be grounds for rejection.

For accepted papers, at least one author must attend the workshop.

Important Dates

Paper submission deadline: March 21, 2023 – 11:59pm AoE (extended, was: March 02, 2023; was: March 15, 2023)
Notification: April 25, 2023 (delayed, was: April 24, 2023; was: April 10, 2023)
Camera-ready: May 08, 2023
Workshop: July 03, 2023

We may be willing to grant small extensions to the submission deadline. Please reach out proactively if you need a few extra day to finalise your SILM 2023 submission: silm-workshop@inria.fr

Workshop Organization

Program Chairs

Contact email: silm-workshop@inria.fr

Publicity

Program Committee

  • Pascal Cotret, ENSTA Bretagne
  • Chris Dalton, HP Labs
  • Lesly-Ann Daniel, KU Leuven
  • Merve Gülmez, Ericsson Research/KU Leuven (Publicity)
  • Karine Heydemann, LIP6
  • Guillaume Hiet, CentraleSupélec/Inria (Co-Chair)
  • Vianney Lapôtre, Univ. South Brittany
  • Clémentine Maurice, CNRS
  • Jan Tobias Mühlberg, ULB/KU Leuven (Co-Chair)
  • Cristofaro Mune, Raelize B.V.
  • Kaveh Razavi, ETH Zurich
  • Simon Rokicki, ENS Rennes
  • Shweta Shinde, ETH Zurich
  • Volker Stolz, HVL
  • Marcus Voelp, Uni Luxembourgh
  • Pierre Wilke, CentraleSupélec/Inria
  • Yuval Yarom, University of Adelaide

Session-1: Microarchitectural Attacks and Defences in Microcontrollers

A Hybrid Solution for Constraint Devices to Detect Microarchitectural Attacks

Authors: Nikolaos Foivos Polychronou, Pierre-Henri Thevenon, Maxime Puys and Vincent Beroulle

Abstract: We are seeing an increase in cybersecurity attacks on resource-constrained systems such as the Internet of Things (IoT) and Industrial IoT (I-IoT) devices. Recently, a new category of attacks has emerged called microarchitectural attacks. It targets hardware units of the system such as the processor or memory and is often complicated if not impossible to remediate since it imposes modifying the hardware. In default of remediation, some solutions propose to detect these attacks. Yet, most of them are not suitable for embedded systems since they are based on complex machine learning algorithms. In this paper, we propose an edge-computing security solution for attack detection that uses a local-remote machine learning implementation to find an equilibrium between accuracy and decision-making latency while addressing the memory, performance, and communication bandwidth constraints of resource-constrained systems. We demonstrate effectiveness in the detection of multiple microarchitectural attacks such as Rowhammer or cache attacks on an embedded device with an accuracy of 98.75% and a FPR near 0%. To limit the overhead on the communication bus, the proposed solution allows to locally classify as trusted 99% of the samples during normal operation and thus filtering them out.

Paper: silm2023-constrained.pdf

Work in Progress: Thwarting Timing Attacks in Microcontrollers using Fine-grained Hardware Protections

Authors: Jean-Loup Hatchikian-Houdot, Nicolas Gaudin, Pascal Cotret, Frédéric Besson, Guy Gogniat, Guillaume Hiet, Vianney Lapôtre and Pierre Wilke

Abstract: Timing side-channels are an identified threat for security critical software. Existing countermeasures have a cost either on the hardware requirements or execution time. We focus on low-cost microcontrollers that have a very low computational capacity. Although these processors do not feature out-of-order execution or speculation, they remain vulnerable to timing attacks exploiting the varying latencies of ALU operations or memory accesses. We propose to augment the RISC-V ISA with security primitives that have a guaranteed timing behavior. These primitives allow constant time ALU operations and memory accesses that do not alter the state of the cache. Our ap- proach has a low overhead in terms of hardware cost, binary code size, and execution time both for the constant time secure program and other programs running concurrently on the same hardware.

Paper: silm2023-cache-protection.pdf
Slides: silm2023-cache-protection-slides.pdf

Emulating Side Channel Attacks on gem5: Lessons learned

Authors: Lilian Bossuet, Vincent Grosso and Carlos Andres Lara Nino

Abstract: Side channel attacks (SCA) have the potential of disrupting the trust of the users on computing platforms and cryptographic algorithms. The main challenge in the design of countermeasures against such threats is that an evaluation of their effectiveness can only be performed after they have been implemented. By that point, significant resources would have been invested in the creation of a prototype. Moreover, the large volume of combinations from all the potential target algorithms and computing systems complicates a systematical analysis. It is necessary to find strategies to simplify and systematize the study of SCAs and their countermeasures. gem5 is a cycle-accurate simulator which offers the possibility to emulate a broad range of computing architectures. Beyond the functional verification, this tool computes multiple physical statistics from the simulated system. In this paper, we discuss the lessons learned from using gem5 to simulate SCAs on an ARM system. Our work shows that while there is a correlation between the data and the reported statistics, there are significant challenges that must be addressed to improve the use of gem5 for the emulation of physical phenomena.

Paper: silm2023-gem5.pdf

Invited Talk: Virtualization-assisted Operating System Security

Speaker: Sergej Proskurin

Abstract: Virtualization technology has undergone a paradigm shift, with a renewed focus on system security. This shift inspired researches to repurpose modern virtualization extensions to form novel virtualization-assisted primitives for dynamic binary analysis and operating system security. This talk explores the potential of virtualization technology for system security and how we can alleviate the strict separation between operating systems and virtual machine monitors to empower systems with advanced security primitives.

Speaker's Bio: Sergej Proskurin works as a Senior Security Engineer at BedRock Systems, specializing in virtualization-assisted operating system security. He received his Ph.D. in Computer Science from the Technical University of Munich. His research interests cover a wide range of low-level topics. In particular, he is passionate about operating system design and leveraging virtualization technology for dynamic binary analysis and operating system security. In the past, Sergej actively contributed to open source projects, including the Xen Project hypervisor and the black-box binary analysis system DRAKVUF.

Slides: silm2023-slides-sergej.pdf

Session-2: Attacks and Defences for Crypto Implementations

Faulting original McEliece’s implementations is possible -- How to mitigate this risk?

Authors: Vincent Giraud and Guillaume Bouffard

Abstract: Private and public actors increasingly encounter use cases where they need to implement sensitive operations on mass-market peripherals for which they have little or no control. They are sometimes inclined to attempt this without using hardware-assisted equipment, such as secure elements. In this case, the white-box attack model is particularly relevant and includes access to every asset, retro-engineering, and binary instrumentation by attackers. At the same time, quantum attacks are becoming more and more of a threat and challenge traditional asymmetrical ciphers, which are treasured by private and public actors. The McEliece cryptosystem is a code-based public key algorithm introduced in 1978 that is not subject to wellknown quantum attacks and that could be implemented in an uncontrolled environment. During the NIST post-quantum cryptography standardization process [17], a derived candidate commonly referred to as classic McEliece was selected. This algorithm is however vulnerable to some fault injection attacks while a priori, this does not apply to the original McEliece. In this article, we thus focus on the original McEliece cryptosystem and we study its resilience against fault injection attacks on an ARM reference implementation [18]. We disclose the first fault injection based attack and we discuss on how to modify the original McEliece cryptosystem to make it resilient to fault injection attacks.

Paper: silm2023-mceliece.pdf
Slides: silm2023-mceliece-slides.pdf

Combined Internal Attacks on SoC-FPGAs: Breaking AES with Remote Power Analysis and Frequency-based Covert Channels

Authors: Anis Fellah Touta, Lilian Bossuet and Carlos Andres Lara-Nino

Abstract: In recent years, the field of side-channel analysis has observed a revolution in the design of the attack methodology. Conventional approaches which require the use of highly specialized equipment like oscilloscopes and spectrum analyzers, despite highly precise, might be regarded as impractical in some scenarios. On the other hand, the use of less-accurate internal sensors which can monitor the power footprint of a circuit has risen in popularity. Delay sensors have shown promising results. These structures are interesting since they can be implemented from regular hardware resources available in most circuits. This means that components already available in the target platform might be leveraged to implement a side-channel attack. Moreover, it has been shown that is not necessary to have direct access to the platform to carry out such an attack; which implies that if there is a remote link such as Ethernet, an adversary might be able to perform Remote Power Analysis (RPA) of the system. So far, the main challenge for the success of this kind of attack is the problem of cutting and aligning the power traces. This is usually achieved through secondary digital channels which carry some trigger information. In this paper, we simplify the conditions for an RPA attack to take place. Namely, our method mitigates the need for connecting digital triggers to the remote sensor. We demonstrate this approach by performing a successful key recovery on a hardware implementation of AES

Paper: silm2023-soc-aes.pdf

Discussion: The Future of SILM

Where do we want to go with the SILM workshop?

Session-3: Side Channels, Static & Dynamic Analysis

Practical Deep Learning-Based Acoustic Side Channel Attack on Keyboards

Authors: Joshua Harrison, Ehsan Toreini and Maryam Mehrnezhad

Abstract: With recent developments in deep learning, the ubiquity of microphones and the rise in online services via personal devices, acoustic side channel attacks present a greater threat to keyboards than ever. This paper presents a practical implementation of a state-of-the-art deep learning model in order to classify laptop keystrokes, using a smartphone integrated microphone. When trained on keystrokes recorded by a nearby phone, the classifier achieved an accuracy of 95%, the highest accuracy seen without the use of a language model. When trained on keystrokes recorded using the video-conferencing software Zoom, an accuracy of 93% was achieved, a new best for the medium. Our results prove the practicality of these side channel attacks via offthe- shelf equipment and algorithms. We discuss a series of mitigation methods to protect users against these series of attacks.

Paper: silm2023-acoustic.pdf

TimeInspector: A Static Analysis Approach for Detecting Timing Attacks

Authors: Fatih Durmaz, Nureddin Kamadan, Melih Taha Öz, Musa Unal, Arsalan Javeed, Cemal Yilmaz and Erkay Savas

Abstract: We present a static analysis approach to detect malicious binaries that are capable of carrying out a timing attack. The proposed approach is based on a simple observation that the timing attacks typically operate by measuring the execution times of short sequences of instructions. Consequently, given a binary, we first construct the control flow graph of the binary and then determine the paths between the pairs of time readings, on which a suspiciously low number of instructions might be executed. In the presence of such a path, we mark the binary as potentially malicious and report all the suspicious paths identified. In the experiments, where a collection of benign and malicious binaries were used, the proposed approach correctly detected all the malicious binaries with an accuracy up to 99.5% and without any false negatives.

Paper: silm2023-timeinspector.pdf

Conception and implementation of a language dedicated to virtual machine introspection

Authors: Lionel Hemmerlé, Jean-Christophe Prévotet, Guillaume Hiet, Frédéric Tronel and Pierre Wilke

Abstract: When using a Host-based Intrusion Detection System (HIDS), we need to protect it against attackers who manage to access a high privilege level. For that, we propose to use virtualization extensions: the protected system can be placed inside a Virtual Machine (VM) and the HIDS in the hypervisor. In this case, even if the VM containing the protected system is entirely compromised by an attacker, including the virtualized operating system, the IDS will still be functional. However, when the HIDS is located in the hypervisor, although it can access the VM memory and intercept all its communication with the hardware, it loses all the abstractions given by the virtualized operating system. To cross this semantic gap, we propose to create a new language that can be used by the VM to write and send programs to the hypervisor. Being produced by the virtual machine itself, we assume that these programs will have the necessary level of knowledge about the depths of the operating system used by the virtual machine. The hypervisor will process those programs and interpret them to detect intrusions. Besides, since those programs came from an untrusted source (the VM) and are executed in the hypervisor, we discuss some security constraints that must be enforced by our solution to ensure that it does not introduce new vulnerabilities in the hypervisor. We already implemented two kernel rootkits that can hide a process from the userspace in the VM, and we created a detection mechanism that receives from a VM a list of memory areas that must be monitored by the hypervisor to detect the two rootkits that we have implemented.

Paper: silm2023-introspection.pdf

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